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A3904 Low Voltage Voice Coil Motor Driver
Features and Benefits
Fixed I2C logic thresholds 8-bit D-to-A converter 500 A resolution Low voltage I2C serial interface Low current-draw sleep mode 2.4 to 5.5 V operation 2 mm x 1.5 mm, 0.38 mm nominal overall height DFN 1.1 mm x 0.7 mm, 0.5 mm maximum overall height WLCSP 1.1 mm x 0.7 mm, 0.33 mm nominal overall height bare die
Description
The A3904 is a voice coil motor (VCM) driver, with an I2C-compatible serial interface. Designed for camera autofocus and zoom applications, this high accuracy digital IC is provided in small packages ideal for portable devices. Its operating voltage range is 2.4 to 5.5 V, and its maximum output current is 127 mA. Output current is programmed via the I2C interface, in 500 uA increments, with clock rates up to 400 kHz. I2C inputs set the internal D-to-A converter output voltage that is the reference for linear current control via a MOSFET output sink transistor. To conserve battery power, a logic low signal on the SLEEPZ input disables the output MOSFET and reduces the supply current to <0.5 A. A3904 internal protection features include thermal shutdown and undervoltage lockout. Logic input levels are independent of the supply voltage. The operating temperature range is -40C to 85C. The A3904 is available at three packaging levels: bare die on wafer (suffix CW); bumped wafer level chip scale package (WLCSP) (suffix CG); and complete thin profile (0.38 mm nominal overall height) DFN package, with NiAuPd leadframe plating and an exposed tab for enhanced thermal dissipation (suffix EW).
Packages:
1.5 mm x 2 mm DFN (EW package)
1.1 mm x 0.7 mm WLCSP (CG package)
Not to scale
Bare die (CW package)
Functional Block Diagram
1.8 V 2.4 to 5.5 V
VDD
IOUT
1.8 k 1.8 k
I2C Master
SDA SCL
Bandgap Ref
8 Bit DAC
I2C Serial Interface
2.4 GND
I2C Slave
SLEEPZ PAD EW only
3904-DS, Rev. 2
A3904
Low Voltage Voice Coil Motor Driver
Selection Guide
Part Number
A3904ECW A3904ECGTR A3904EEWTR-P Wafer 4000 pieces per reel 3000 pieces per reel
Packing
Package
Bare die Bumped wafer-level chip-scale package (WLCSP) Leadless package (DFN)
Pb-Free
Yes Pb-free chip with high-temperature solder balls (RoHS compliant) Yes; NiAuPd leadframe plating
Absolute Maximum Ratings
Characteristic
Supply Voltage Logic Input Voltage Range Operating Ambient Temperature Maximum Junction Temperature Storage Temperature
Symbol
VDD VIN TA TJ(max) Tstg Range E
Notes
Rating
6 -0.3 to VDD+0.3 -40 to 85 150 -55 to 150
Units
V V C C C
Thermal Characteristics
Characteristic Symbol Test Conditions*
EW package, 4-layer PCB based on JEDEC standard
Rating
64
Units
C/W
Package Thermal Resistance, Junction RJA to Ambient *For additional information, refer to the Allegro website.
Pin-out Diagrams CG Package EW Package
A1 B1 A2 B2 A3 B3
SDA SCL VDD 1 2 3 PAD 6 5 4 SLEEPZ IOUT GND
Orientation mark on ball side
Terminal List
Number EW 1 2 3 4 5 6 PAD CG A1 A2 A3 B3 B2 B1 - Name SDA SCL VDD GND IOUT SLEEPZ - Description I2C data input/output I2C clock Power supply Ground Sink drive output Standby mode control Exposed thermal pad (tie to GND)
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
ELECTRICAL CHARACTERISTICS Valid at TA= 25C, VDD = 2.4 to 5.5 V, unless otherwise noted
Characteristics General Supply Current UVLO Enable Threshold UVLO Hysteresis Thermal Shutdown Temperature Thermal Shutdown Hysteresis Power-Up Delay D-to-A Converter Resolution LSB Relative Accuracy LSB Differential Nonlinearity Maximum Output Current Gain Error Gain Error Drift* Offset Error Output Output Voltage Range Output On Resistance I2C Interface Bus Free Time Between Stop and Start Hold Time Start Condition Setup Time for Repeated Start Condition SCL Low Time SCL High Time Data Setup Time Data Hold Time Setup Time for Stop Condition Logic Input Low Level (SDA, SCL pins) Logic Input High Level (SDA, SCL pins) Input Hysteresis (SDA, SCL pins) SLEEPZ Input Low Level SLEEPZ Input High Level Logic Input Current Output Voltage (SDA pin) Clock Frequency (SCL pin) Output Fall Time (SDA pin) tBUF thdSTA tsuSTA tLOW tHIGH tsuDAT thdDAT tsuSTO VIL VIH Vhys VinSLP VinSLP IIN VOL fCLK tfO VIH to VIL VIN = 0 V to VDD ILOAD = 1.5 mA 1.3 0.6 0.6 1.3 0.6 100 0 0.6 - 1.26 - - 1.5 -1 - - - - - - 100 - - 0 - - - - - - - - - - - - - - - 900 - 0.84 - - 0.7 - 1 0.36 400 250 s s s s s ns ns s V V mV V V A V kHz ns VOUT RDS(on) RSENSE + RSINK, IOUT = 127.5 mA 0.500 - - 3 VDD-0.1 - V Res INL DNL Imax errA errA IerrOS Target = 500 A / LSB Code = 16 to 255, Endpoint method Guaranteed monotonic Code = 255 TJ = 25C, Code 16 to 255, VDD = 2.6 to 3.0 V TJ = -40C to 125C Code = 1 Code = 16 - - - - -10 - 0 0.5 8 4 - 127.5 <3 0.2 1 - - - 1 - 10 - 5 - bit LSB LSB mA %FS LSB/C mA mA IDD VUV(th) VUV(hys) TJTSD .TJTSD(hys) td(on) Temperature increasing TJTSD(hys) = TJTSD - TJ(recover) - Sleep mode (SLEEPZ = Low) VDD rising - - 100 - - - 0.5 <100 2.1 - 165 15 10 2 500 2.395 - - - - mA nA V mV C C s Symbol Test Conditions Min. Typ. Max. Units
*Guaranteed by design and characterization, not production tested
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
I2C Interface Timing Diagram
tsuSTA thdSTA tsuDAT thdDAT tsuSTO tBUF
SDA
SCL
tLOW
tHIGH
Write Register Bit Definition and Timing Diagram
Start Address SDA 0 0 0 1 1 x x 0 AK D7 D6 D5 Write Acknowledge (from A3904) Control Data D4 D3 D2 D1 D0 AK Acknowledge (from A3904) Stop
SCL
1
2
3
4
5
6
7
8
9
I2C Control Register Bit Definition
Bit
0 1 2 3 4 5 6 7
Name
D0 D1 D2 D3 D4 D5 D6 D7
Function
DAC LSB
DAC MSB
A3904 Slave Address Bit Definition Bit 0
0
1
0
2
0
3
1
4
1
5
x
6
X
7
1 0
Operation
Read Write
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
Functional Description
The A3904 output current is controlled by programming the D-toA converter value via the I2C serial port. The target output current can be calculated by: IOUT = DAC x 500 A , where DAC = 1 to 255. Code = 0 is a disable state for the output sink drive. The DAC will be set to code = 0 upon power-up or a fault condition on VDD. in the following sequence:
1. Start Condition. Defined by a negative edge on the SDA line, while SCL is high. 2. Address Cycle. 7 bits of address, plus 1 bit to indicate write (0) or read (1), and an acknowledge bit. The address setting is 0x18, 0x1A, 0x1C or 0x1E. 3. Data Cycles. Write 8 bits of data that address the internal Control register, followed by an acknowledge bit. 4. Stop Condition. Defined by a positive edge on the SDA line, while SCL is high.
Except to indicate a Start or Stop condition, SDA must be stable while the clock is high. SDA can only be changed while SCL is low. It is possible for the Start or Stop condition to occur at any time during a data transfer. The A3904 always responds by resetting the data transfer sequence. The Read/Write bit is set low to indicate a write cycle. Multiple writes are allowed before issuing a Stop condition. There are no readback functions incorporated into the A3904. The master monitors for an acknowledge pulse to determine if the slave device is responding to the address byte sent to the A3904. When the A3904 decodes the 7-bit address field as a valid address, it responds by pulling SDA low during the ninth clock cycle. During a data write from the master, the A3904 pulls SDA low during the clock cycle that follows the data byte, in order to indicate that the data has been successfully received. After sending either an address byte or a data byte, the master device must release the SDA line before the ninth clock cycle, in order to allow this handshaking to occur.
SLEEPZ A logic low input disables all of the internal circuitry
and prevents the IC from draining battery power.
Output Range The voltage on the IOUT pin should be greater
than 500 mV to guarantee the accuracy and linearity of the programmed current. The output voltage is a function of the battery voltage, motor resistance, and the programmed load current.
Clamp Diode When the output is turned off, the load inductance causes the output voltage to rise. A clamp diode, from IOUT to VDD, is integrated in the IC to ensure that the output voltage remains at a safe level.
I2C Interface This is a serial interface that uses two bus lines,
SCL and SDA, to access the internal Control registers. Data is exchanged between a microcontroller (master) and the A3904 (slave). The clock input to SCL is generated by the master, while the SDA line functions as either an input or an open drain output, depending on the direction of the data. The I2C input thresholds do not depend on the VDD voltage of the A3904. The levels are fixed at approximately 1 V. The fixed levels allow the SDA and SCL lines to be pulled-up to a different logic level than the VDD supply of the 3904.
Timing Considerations The control sequence of the communication through the I2C interface is composed of several steps
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
Application Information
Headroom The current may not reach the programmed level
if there is not adequate headroom in the output circuit. The IC output voltage must be over 500 mV to guarantee normal linear operation. VDD, ILOAD, and RLOAD can be adjusted to ensure that the device operates in the linear range. If the equation shown below is not satisfied, the load current will be limited by the series impedance, and may not reach the programmed level VDD(min) - RLOAD(max) x IOUT(max) 500 mV . be positive for each incremental step, according to the following formula: DNL = (IOUT(n+1) - IOUT(n) ) / LSB - 1 (LSB) . where n is in the range 16 to 255. Offset error The measured output current at input Code = 16, compared to the ideal value according to the transfer function (8 mA). Gain Error The difference in the slopes of the ideal transfer function and the actual transfer function. The gain error is calculated by subtracting out the offset error, at Code = 16, from the actual transfer function. This calculated value is compared to the ideal transfer function and reported as a percentage of the ideal full scale value (127.5 mA). See figure 2. Gain Error Drift The change in slope of the transfer function due to temperature, expressed as LSB/C.
IOUT Errors
Relative accuracy (INL) This error is calculated by measuring the worse case deviation from a straight line, defined from end points. The straight line end points are defined by the actual measured values at Code = 16 and Code = 255. See figure 1. Differential nonlinearity (DNL) A measure of the monotonicity of the D-to-A converter. The slope of the line must always
127.5 INL 96.0 IOUT (mA) 127.5 IOUT (mA)
Offset Error Gain Error
64.0
32.0
0 0 16 128 Code Straight line between measured Codes 16 and 255 Relative Accuracy ( Codes 16-255), errors exaggerated for clarity 255
0 0 16 128 Code Ideal DAC Actual DAC, errors exaggerated for clarity Calculated Gain Error, Offset Error removed 255
Figure 1. Relative accuracy error
Figure 2. Gain error
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
CG Package, 6-Bump WLCSP
1.055 1 2 3 X 148 A 0.370 B 1 2 3
A
B 0.705
B
0.370 0.740 C SEATING PLANE 6X 0.05 C 0.170 A Die orientation mark B A C Terminal #A1 mark area Reference view of typical layout for solder pads All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances 0.500 MAX C PCB Layout Reference View
All dimensions nominal, not for tooling use Dimensions in millimeters Exact configuration at supplier discretion within limits shown
B
0.370 A
0.167 0.158
1 0.370
2
3
0.740
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
CW Package, 8-Bondpad Bare Die
0.330
Die Alignment on Wafer Die Pitch 1.100 x 0.750
1.055 8X0.065 B
B 8X0.065 0.705
A
Top layer polymide All dimensions nominal; not for tooling use Dimensions in millimeters Exact configuration at supplier discretion within limits shown A Die orientation mark area B Bond pad opening in passivation IOUT SLEEPZ SCL SDA SCL GND IOUT VDD
Bondpad*
GND IOUT_1 IOUT_2 SDA SCL_1 SCL_2 SLEEPZ VDD
X Coordinate (m)
444.5 408.7 319.95 -421.65 136.3 -421.65 -421.65 396.15
Y Coordinate (m)
269.45 9.7 233.55 -242.6 -243.7 9.0 242.6 -238.5
*Redundant bondpads are electrically equivalent and provide alternative locations for bonding.
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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A3904
Low Voltage Voice Coil Motor Driver
EW Package, 6-Contact DFN
1.50 0.15 6
0.50 6
0.30
2.00 0.15 A 1 1.10 7X D 0.08 C SEATING PLANE 0.38 0.02 0.50 1 0.25 0.05
0.70
1.575
1
0.325
C
PCB Layout Reference View
For Reference Only (similar to JEDEC Type 1, MO-229"X2"BCD) Dimensions in millimeters Exact case and lead configuration at supplier discretion within limits shown 1.25 0.05 A Terminal #1 mark area B Exposed thermal pad (reference only, terminal #1 identifier appearance at supplier discretion) C Reference land pattern layout (reference IPC7351 SON50P200X200X100-9M); All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5) D Coplanarity includes exposed thermal pad and terminals
B
0.70 0.02
+0.055 0.325 -0.045
6 1.10 0.10
Copyright (c)2007-2008, Allegro MicroSystems, Inc. The products described here are manufactured under one or more U.S. patents or U.S. patents pending. Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current. Allegro's products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. For the latest version of this document, visit our website: www.allegromicro.com
Allegro MicroSystems, Inc. 115 Northeast Cutoff Worcester, Massachusetts 01615-0036 U.S.A. 1.508.853.5000; www.allegromicro.com
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